The semiconductor industry is currently amidst a paradigm shift from aluminum interconnects with silicon dioxide (“SiO2”) interlayer dielectrics to copper interconnects with interlayer dielectrics having dielectric constants lower than that of silicon dioxide (“low-k dielectrics”). This change has been mandated by decreasing critical dimensions, as from the current 0.18 micron technology node to state-of-the-art 0.13 micron and smaller technology nodes.
Two of the performance limiting factors of aluminum/silicon dioxide interconnect/dielectric technology are the resistivity of aluminum and dielectric constant of SiO2. As the integrated circuit feature size decreases, the distance between interconnect layers and conducting pathways decreases. Since the capacitance between the interconnects and pathways is inversely proportional to the distance, all else being equal, decreasing feature sizes increases capacitance. Given that an integrated circuit's performance is limited by resistance/capacitance interactions (“RC constant”), capacitive coupling, and power consumption, lowering either the capacitance, resistance, or both permits faster integrated circuit speeds for a given critical dimension.
The switch from aluminum to copper interconnects equates to a 37% decrease in resistivity and improves the RC constant for a given capacitance. However, the switch from SiO2 to lower dielectric constant dielectrics (to decrease the capacitance factor of the RC constant) is not so well defined. There are myriad choices for the dielectric material and deposition process.
An early forerunner in low-k dielectrics was fluorine doped silicon oxide, or fluorosilicate glass (“FSG”). The appeal was that an FSG film could be deposited in the same manner as the undoped film, allowing the use of the same processing techniques and machines. However, the dielectric constant of fluorinated silicon dioxide is not substantially lower (3.3-3.5) than undoped silicon dioxide (3.9-4.2). Further, fluorinated silicon oxide absorbs water and has mechanical properties that may limit its use as a low-k dielectric.
Another popular material is carbon doped oxide, or organosilicate glass (“OSG”). Generally speaking, the OSG films have an SiwCxOyHz structure wherein the tetravalent silicon has a variety of organic group substitutions. The most common substitution is a methyl (CH3) group provided by an organic precursor gas like trimethylsilane or tetramethlysilane (“3MS” and “4MS” respectively). In OSG the amorphous SiO2 network is sporadically interrupted by the organic group, decreasing the density of the film. Like with FSG, the lower density of OSG compared to undoped SiO2 decreases the dielectric constant. Also like FSG, OSG exhibits certain thermal and mechanical difficulties with current semiconductor processing techniques. Though widely accepted as a low-k dielectric solution, OSG does not offer significantly low dielectric constant values.
FIG. 1 illustrates a cross section of a copper dual-damascene architecture utilizing a low-k interlayer dielectric (“ILD”). A substrate 100 contains any variety of semiconductor devices well known to those skilled in the art as represented rudimentarily by source and drain regions 101, dielectric 120, and gate 121 of a metal oxide semiconductor (“MOS”) transistor. Interconnect levels 104, 106, and 108 are representative of, for example, the trench level of a copper dual-damascene interconnect structure, for which via levels 103, 105, and 107 provide electrical contact between interconnect layers and between interconnect layers and semiconductor devices. ILD layers 109 through 114 are formed of low-k dielectric material. The ILDs not only isolate interconnects on different layers, but also isolate interconnects on the same layer. Passivation layer 115 completes the interconnect stack.
FIG. 2a illustrates a cross section of a substrate 200 utilizing a via-first, dual-damascene process. Specifically, FIG. 2a illustrates substrate 200 following via and trench feature etches and prior to an antireflective coating (“ARC”) 203 layer removal from the planar surface of an ILD 202 and from within the previously etched via feature. Substrate 200 can be any material onto which an additional interconnect system (dielectric, via, and trench layers) will be added. For example, substrate 200 could be device-containing silicon, or it could be another interconnect system as illustrated by FIG. 1. Etch stop 201 is a deposited material (e.g., silicon nitride, silicon carbide, and silicon oxy nitride) that aids etch selectivity during certain steps of the copper dual-damascene process. Exposure to plasma used to etch the via and trench features has removed surface organic groups of ILD 202 as illustrated by depleted dielectric surface 204. Without surface organic groups, the dielectric constant of ILD 202 is greater than that of the pristine ILD 202 material. The depleted dielectric surface 204 is unprotected against fluoride-based aqueous chemistries to which it may be exposed during subsequent processing steps.
FIG. 2b illustrates substrate 200 of FIG. 2 following the wet etch step to remove ARC 203 layer from both the surface of ILD 202 and from within the previously etched via feature. Fluoride-based aqueous chemistries during the wet etch of ARC 203 and subsequent cleaning steps have further damaged the surface of ILD 202. As noted with reference to FIG. 2a, the plasma used to etch the via and trench features has removed ILD 202 surface organic groups, making the resulting unprotected, hydrophilic surface of ILD 202 more vulnerable to attack by the wet etch chemistries. Between the damage caused by the via and trench plasma etches (specifically the removal of the surface organic groups) and the ARC 203 wet etch, ILD 202 has been rendered useless for both physical and chemical reasons as illustrated by damaged dielectric surface 205. Not only has the dielectric constant of ILD 202 increased, but the critical dimension (the smallest separation of layers, features, etc. tolerable for functional devices, shown as the ILD 202 thickness separating two trench features) has also been compromised as illustrated by threatened critical dimension 206.